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From Timing Analysis to Vulnerability: How WCET Flaws Can Lead to Exploits in Real-Time Systems

UUnknown

2026-02-11

11 min read

Timing-analysis gaps in ECUs and PLCs open paths to stealthy exploits; learn how WCET flaws become attacks and what security teams must do now.

When execution time is safety: why timing analysis gaps keep CISOs up at night

Real-time systems — in cars, industrial controllers and robotics — are only as safe as the assumptions you make about how long code will run. In 2026, automobile ECUs and PLCs are more software-defined, multi-core and networked than ever, and that complexity has widened the attack surface for timing-based threats. Security and engineering teams now face a dual problem: gaps in worst-case execution time (WCET) analysis that create unanticipated deadline misses, and novel exploitation techniques that convert those timing gaps into reliable attack vectors. This investigative piece links timing-analysis failures to concrete exploitation scenarios in automotive and ICS environments and gives security teams an operational playbook to close the gap.

The stakes in 2026: why WCET and timing security matter now

Over the last 18 months the industry accelerated two parallel trends that make timing security a top-tier threat vector:

Software-defined vehicles and centralized compute: consolidation of ECUs to zonal and domain controllers increases resource sharing and inter-task interference.
Regulatory and standards pressure: ISO 26262 and ISO/SAE 21434 continue to drive safety and cybersecurity integration, while IEC 62443 shapes industrial requirements. Vendors must now provide verifiable timing guarantees as a component of both safety and security compliance.

Vendor activity reflects this pressure: in January 2026 Vector Informatik acquired StatInf’s RocqStat timing-analysis technology to integrate WCET estimation into VectorCAST, signaling that timing analysis is moving from specialist research labs into mainstream automotive toolchains. That integration matters: a unified verification and timing environment lets teams treat timing correctness as part of their CI/CD safety gate rather than an afterthought.

How timing-analysis gaps turn into real exploits

To understand how an abstract timing error becomes an exploit, you must follow the chain: inadequate analysis → latent non-determinism → attacker-controlled perturbation → safety or confidentiality breach. Below are the primary exploitation patterns we observed in research and field analysis in 2025–2026.

1. Underestimated WCET → missed deadlines and unsafe states

WCET underestimations occur when static analysis tools or test harnesses do not account for worst-case caches, branch mispredictions, interrupts, DMA contention, or multi-core interference. An attacker who can increase contention (via a compromised process, malicious firmware update, or manipulated input stream) can push a critical task past its deadline.

Practical scenario (automotive): a vehicle's braking controller is consolidated into a zonal controller sharing CPU time with an infotainment or OTA agent. WCET analysis underestimated shared L2 cache interference. An attacker triggers a high-frequency sensor input pattern that causes heavy cache thrashing in a benign-looking process, forcing the braking task to miss its deadline and enter a degraded braking regime.

Practical scenario (ICS): a PLC controlling a chemical valve is scheduled on a multi-core edge gateway. Unaccounted DMA transfers from a misconfigured HMI cause latency spikes, so the valve actuation misses its real-time window and a safety interlock fails.

2. Timing channels and covert exfiltration

Timing channels are low-and-slow data exfiltration techniques where an attacker modulates execution time, network latency or scheduling patterns to encode data. In 2026, as diagnostic and telemetry interfaces grow richer, so does the opportunity for timing side-channels.

3. Resource contention → covert Denial-of-Service

Modern systems rely on shared buses, caches and networks. Attackers can purposefully create contention (memory bandwidth, DMA, interrupts) to inflate the effective WCET of other tasks, turning a timing-analysis gap into a reliable DoS. Unlike volumetric DoS, timing DoS can be surgical: disrupt control loops without obvious network noise.

4. Exploiting non-determinism in COTS stacks

Commercial RTOSes and general-purpose OS components introduce jitter (dynamic scheduling, DMA drivers, SD card I/O). Combined with modern hardware features (out-of-order execution, speculative execution and deep caches), this non-determinism widens WCET tails. Attackers who probe and profile a system remotely can identify predictable windows to launch more invasive payloads — for instance injecting packets precisely when a safety task is starved.

Three investigative examples: automotive, industrial, and cross-domain

Below are three short, evidence-based investigative vignettes based on red-team assessments and observed campaign artifacts from late 2025 and early 2026.

Automotive: zonal compute and the ‘silent scheduler’ attack

In a third-party audit of a zonal controller, analysts found that an OTA management process periodically performed large flash writes with high-priority interrupts disabled. WCET tests run in isolation gave the flash-write handler a safe bound, but build-time tests did not include concurrent CAN traffic and Ethernet AVB bursts used by ADAS sensors. A red team instrumented the CAN bus to flood small high-priority frames timed to coincide with flash activity; the combined interference caused scheduling inversion in the ADAS input pipeline. Result: delayed object detection messages and a transient ADAS disablement that went undetected by existing monitors.

ICS: time-synchronized denial of safety-critical actuation

An attacker with initial foothold on a plant engineering workstation pushed malformed HMI updates that triggered periodic high-priority logging on the control gateway. Because the control loop depended on sub-millisecond actuation windows and timing analysis had not modeled networked time sync jitter (PTP), the control system intermittently missed control cycles. In a conservative plant mode, this triggered spurious emergency shutdowns.

Cross-domain: covert data leak via telemetry jitter

A threat actor on a supply-chain managed maintenance channel used micro-jitter in OTA acknowledgements to encode pieces of configuration data. The recipient on the adversary infrastructure reconstructed the data from timing intervals across multiple maintenance sessions. Because the pattern mimicked normal telemetry jitter, detection took weeks.

Why existing defenses fail

WCET tools are often separate from the CI/CD pipeline and are used late in development or only for high-critical tasks.
Runtime monitors focus on functional invariants but not timing invariants (P99/P999 latencies, deadline miss rates).
Security testing (fuzzing, pentesting) rarely includes timing-aware adversarial models that purposefully induce contention or jitter.
Toolchain and library behavior (dynamic allocation, interrupts) are under-modeled during static analysis.

A practical mitigation playbook for security and engineering teams

The good news: most timing vulnerabilities are preventable or detectible with disciplined engineering and operational telemetry. Below is a prioritized, actionable checklist you can adopt now.

Design-time and procurement

Require timing budgets in architecture documents. Define per-task WCET budgets and explicit margins for multi-core and network interference.
Specify time-aware isolation in procurement: prefer time-triggered architectures, hardware-based partitioning, or hypervisor solutions with real-time scheduling guarantees.
Vendor controls: require suppliers to provide WCET evidence (tool reports, assumptions, instrumentation) and continuity plans for timing tools — the Vector–RocqStat acquisition shows vendor consolidation is underway; insist on traceability.

Build-time: integrate timing verification into CI/CD

Automate WCET analysis as part of builds. Use integrated tools (example: VectorCAST + RocqStat) to block merges where timing regressions are detected.
Timing-aware fuzzing: extend fuzzers to include adversarial workload generators that vary CPU, memory and I/O load while exercising critical code paths.
Regression baselines: store P50/P95/P99/P999 metrics and trace artifacts for each commit to quickly detect drift — treat these artifacts like other compliance records (see guidance on document lifecycle management).

Runtime monitoring and detection

Collect execution-time telemetry: instrument tasks to emit execution time histograms; maintain rolling P95/P99/P999. Tail latency is the primary indicator of an attack or misconfiguration. Use analytics playbooks to operationalize thresholds (see analytics guidance).
Hardware tracing: enable ARM CoreSight/ETM, DWT and PMU counters in production debug builds to capture precise timing and memory access patterns (with privacy controls for field data).
Anomaly rules: create detection rules for sudden increases in deadline-miss rate, sustained growth in tail latency, or repeated cache-miss spikes correlated with task identities.
Runtime enforcement: use watchdogs with graded responses — safe degradation, redundant execution, or quarantine — not immediate hard stops that create new safety risks.

Architectural changes

Mixed-criticality scheduling: implement temporal partitioning (ARINC 653, time-triggered scheduling) to prevent low-criticality tasks from starving high-criticality loops.
Redundancy and voting: run duplicate critical tasks on separate cores or ECUs and compare outputs before actuation.
Network QoS and determinism: apply TSN and strict priority queuing, with PTP guard-banding, to reduce jitter introduction at the network layer.

Operational & incident response

Forensic timing logs: ensure logging includes high-resolution timestamps and task identifiers for deterministic replay during IR — store and protect these logs like other sensitive artifacts (secure workflows help; see secure vault workflows).
Run stress exercises: tabletop and red-team exercises that intentionally create contention and timing anomalies; validate detection and remediation playbooks.
Patch and config control: treat timing-sensitive firmware/driver updates as safety-critical: staged rollouts, canary tests with timers, and telemetry thresholds before broad deployment.

Concrete KPIs and detection thresholds

Make timing metrics actionable by defining thresholds and SLAs:

Deadline miss rate: target < 0.01% for hard real-time tasks; alert > 0.1% over 1 minute.
Tail latency (P999): define absolute microsecond/millisecond ceilings per task and alert on 3x increases.
Cache-miss anomalies: baseline per-task L1/L2 miss rates; alert on sustained multipliers that correlate with deadline misses.
Execution time variance (sample stddev): track drift and abnormal kurtosis as early indicators of exploitation.

Why unified tooling and standards matter: the Vector–RocqStat example

Standalone timing reports are useful, but too often the assumptions that produced WCET estimates are lost in translation between teams and tools. The 2026 Vector acquisition of RocqStat demonstrates a market shift toward toolchains that unify code testing, verification and timing analysis. That integration provides two security advantages:

Traceability: you can prove which assumptions (cache models, inter-core interference) led to the WCET bound used in a component’s certification — store those artifacts in a managed lifecycle system (document lifecycle guidance).
Automation: timing tests can be executed as part of CI with code changes, preventing regressions that would otherwise turn into runtime vulnerabilities.

“Timing safety is becoming a critical ...” — industry statements in early 2026 reflect that vendors now see timing as both a safety and security control.

Future predictions and trends (2026–2028)

Based on vendor moves, regulatory pressure and observed campaigns, expect the following over the next 24 months:

WCET as a compliance artifact: audits and type approvals will increasingly require WCET evidence and runtime telemetry records for safety-critical releases.
Tool consolidation: additional acquisitions and product integrations will push timing analysis into mainstream development suites — raising baseline quality but also creating monocultures that must be scrutinized. See our note on recent vendor M&A activity for context: cloud vendor merger ripples.
Timing-aware offensive tooling: both red teams and adversaries will adopt timing fuzzers and contention generators, making it imperative to test for these vectors in CI and production. Lightweight labs and edge devices make it easier to prototype these tools (examples exist for local device labs: Raspberry Pi 5 + AI HAT+ 2).
Embedded runtime EDR: expect vendors to introduce lightweight runtime detection agents that include timing anomaly detection designed for resource-constrained devices.

Checklist: 10 immediate actions for security teams

Inventory timing-critical tasks and create a WCET priorities map.
Integrate WCET analysis into CI and block merges on regressions.
Enable high-resolution telemetry and collect P95/P99/P999 metrics in production.
Instrument hardware traces (CoreSight/ETM/PMU) for incident support.
Implement temporal partitioning for mixed-criticality systems.
Run timing-aware fuzzing and red-team contention tests quarterly.
Define KPIs and alert thresholds for deadline misses and tail latency.
Require vendors to deliver WCET assumptions and tool outputs with updates.
Practice incident response with deterministic replay and timing logs.
Adopt graceful degradation and redundant execution for critical actuators.

Closing: treat timing like configuration — because an attacker will

Timing is not an esoteric academic problem anymore. As systems consolidate, networks become deterministic, and regulatory expectations rise, timing-analysis gaps will be one of the next high-leverage vectors for attackers who want stealthy, high-impact effects. The technical debt is fixable: unify WCET tooling into your development pipeline, instrument runtime telemetry, and adopt architectural controls that limit the attacker’s ability to manipulate execution time.

Actionable takeaway: start by adding three measures this quarter — automate WCET checks in CI, deploy tail-latency telemetry for every critical task, and run a timing-aware red-team exercise. Those steps will both reduce your immediate attack surface and provide evidence you can use in audits and supplier reviews.

Call to action

If your team is responsible for vehicle or ICS safety and security, don’t wait until a deadline miss becomes an incident. Download our WCET Security Checklist, schedule a timing-focused red-team exercise, or contact our threat intelligence team for a tailored assessment of your architecture. Close the timing gap before an attacker turns it into a path to exploitation.

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